/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved.
 * File name     :  ddrc_arm_ras_reg_offset.h
 * Description   :  SPU DDRC ram_ras 相关寄存器偏移
 * History       :  2023/04/19 11:05:46 Create file
 */

#ifndef __DDRC_ARM_RAS_REG_OFFSET_H__
#define __DDRC_ARM_RAS_REG_OFFSET_H__

/* ARM_RAS Base address of Module's Register */
#define CSR_ARM_RAS_BASE                     (0x2000)

/******************************************************************************/
/*                      ARM_RAS Registers' Definitions                        */
/******************************************************************************/

#define ARER_ERR_FR_L_REG     (CSR_ARM_RAS_BASE + 0x0)
#define ARER_ERR_FR_H_REG     (CSR_ARM_RAS_BASE + 0x4)
#define ARER_ERR_CTLR_L_REG   (CSR_ARM_RAS_BASE + 0x8)
#define ARER_ERR_CTLR_H_REG   (CSR_ARM_RAS_BASE + 0xC)
#define ARER_ERR_STATUS_L_REG (CSR_ARM_RAS_BASE + 0x10)
#define ARER_ERR_STATUS_H_REG (CSR_ARM_RAS_BASE + 0x14)
#define ARER_ERR_ADDR_L_REG   (CSR_ARM_RAS_BASE + 0x18)
#define ARER_ERR_ADDR_H_REG   (CSR_ARM_RAS_BASE + 0x1C)
#define ARER_ERR_MISC0_L_REG  (CSR_ARM_RAS_BASE + 0x20)
#define ARER_ERR_MISC0_H_REG  (CSR_ARM_RAS_BASE + 0x24)
#define ARER_ERR_MISC1_L_REG  (CSR_ARM_RAS_BASE + 0x28)
#define ARER_ERR_MISC1_H_REG  (CSR_ARM_RAS_BASE + 0x2C)

#endif // __DDRC_ARM_RAS_REG_OFFSET_H__
